AMD's next-gen Zen 6 CPU cores will come in a low-power compact flavour, which should help laptop batteries last even longer

AMD Strix Point APU chip, held in a hand, with the reflected light showing the various processing blocks in the chip die
(Image credit: AMD)

Three years ago, AMD introduced a new type of CPU core for its Zen 4 microarchitecture. The idea behind them was to reduce the amount of die space taken up by a regular core, so that more of them could be packed into a chiplet. The compact design is now a staple part of the Zen family, but it turns out that Team Red has another one on the way for Zen 6.

As reported by Phoronix, a Linux kernel update has been submitted by AMD, with the notes in the kernel mailing list neatly explaining what the new code is for. "This series extends the x86 topology cpu_type classification to support a Low Power core type, in addition to the existing Performance and Efficiency types."

Now, it's worth noting that what AMD calls Performance and Efficiency isn't the same as Intel's terminology. In the case of the former, Performance core types are just your regular Zen blocks: these are the biggest, in terms of die size, and have the highest boost clocks. The Efficiency types are the compact cores (i.e. Zen 4c, Zen 5c), which work exactly like the normal ones, but are smaller in size, often with less L3 cache, and have lower boost clocks.

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As for the upcoming Low Power cores, AMD's Vishal Badole writes: "AMD heterogeneous parts report the core type via CPUID Fn0x80000026 EBX[31:28] (Extended CPU Topology, Core Type). Value 2 identifies a low-power core designed for minimal power consumption during background or idle workloads."

That's very similar to Intel's LPE cores (Low Power Efficiency) that you'll find in its current Panther Lake chips. These are simply E-core clusters that have been tuned to run with a very low power limit, though their boost clocks are only fractionally (100 MHz) down on the regular E-cores.

Zen 4c diagram

Zen 4c is functionally identical to Zen 4 but takes up just half the space. (Image credit: AMD)

However, where AMD's Zen cores all have the same architecture and instruction set, Intel's P- and E-cores are internally quite different. That makes it a bit harder for the chip and operating system to schedule threads correctly, but both configurations rely on a variety of systems and techniques to ensure that low-performance or background task threads are issued to Efficiency cores, with the more demanding ones being sent to Performance cores.

Since there are no Zen 5LP cores in any Ryzen, Threadripper, or Epyc product, it's clear that AMD intends to announce them as part of its Zen 6 launch (though perhaps not immediately). It's also clear as to which product family they'll appear in, and it's Ryzen chips for mobile/low power platforms (i.e APUs).

Many of these already sport compact cores, such as the Ryzen AI 7 350, which has four Zen 5 and four Zen 5c cores; Valve's new Steam Machine uses an AMD CPU that has two Zen 4 and four Zen 4c cores. In both cases, the use of compact cores helps to reduce the overall die size (which improves wafer yields) and reduce chip power consumption.

The introduction of Zen 6LP should help the latter even more, or rather, open up scenarios where the processor is happy to work away with just a handful of watts. That's unlikely to be of much use in handheld gaming PCs, for example, but it should mean that future AMD-powered laptops will have even longer battery lifespans.

I do have one concern, though. If Zen 6 mobile processors are still going to be based on an eight-unit CCX (core complex), there could be some all-out performance regression if some of the Efficiency cores are exchanged for Low Power ones, assuming they have a lower boost clock. That said, there has been plenty of talk that AMD will move to a 12-unit CCX with Zen 6, and if that's also the case for its APUs, then future mobile Ryzen chips could offer the best of every world.

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Nick Evanson
Hardware Writer

Nick, gaming, and computers all first met in the early 1980s. After leaving university, he became a physics and IT teacher and started writing about tech in the late 1990s. That resulted in him working with MadOnion to write the help files for 3DMark and PCMark. After a short stint working at Beyond3D.com, Nick joined Futuremark (MadOnion rebranded) full-time, as editor-in-chief for its PC gaming section, YouGamers. After the site shutdown, he became an engineering and computing lecturer for many years, but missed the writing bug. Cue four years at TechSpot.com covering everything and anything to do with tech and PCs. He freely admits to being far too obsessed with GPUs and open-world grindy RPGs, but who isn't these days?

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