More details of an extra big Intel Nova Lake 'bLLC' CPU die with added cache and designed to take on AMD's X3D chips emerge

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The 'bLLC' CPU die is allegedly 36% bigger than the regular high-performance die.

A close-up, detailed photo of a delidded Intel Core Ultra 200S processor, codenamed Arrow Lake, showing the structures of each tile comprising the processor.
(Image credit: Fritzchen Fritz)

The Intel Nova Lake leaks are coming thick and fast today. Earlier, Nick reported on the apparently outsized power requirements of the dual-CPU-die variant of Nova Lake with 52 cores. Now come claimed details about the equally outsized proportions of the widely rumoured "bLLC" version of the Nova Lake CPU die with added cache memory.

In this context, "bLLC" stands for 'big last level cache' and indicates Intel's response to AMD's X3D V-cache CPUs, such as the Ryzen 7 9800X3D. The difference with Intel's approach is that instead of adding a separate slice of cache memory to the CPU die, as AMD does, Intel is reportedly planning to build the extra cache memory into the die itself.

If true, that will mean the bLLC CPU die will be substantially bigger than the non-bLLC die. And today, we have some apparently leaked numbers to put on that size differential.

According to X-based leaker HXL, the standard Nova Lake die comes in at 110 mm2. But the bLLC version clocks in at 150 mm2, quite a step up. For context, an AMD Zen 5 CPU die measures 71 mm2.

Making comparisons with AMD is complicated, though. The Nova Lake dies contain eight Performance and 16 Efficient cores, while the AMD die has just eight standard Zen 5 cores.

AMD Ryzen 7 9800X3D processor

Intel's Nova Lake bLLC chips will go up against AMD's X3D CPUs. (Image credit: Future)

Meanwhile, the Nova Lake die is claimed to be built on TSMC's N2 silicon node, while Zen 5 is on TSMC N4, which is fully two generations of silicon older. If you're wondering why there's only talk of TSMC silicon, my understanding is that Intel may be farming out production of the larger CPU variants of Nova Lake to TSMC, while producing the smaller ones in-house on its new 18A node.

There is precedent for this approach in Intel's new Panther Lake CPUs. They use the Intel 3 node for the smaller version of the Xe3 iGPU, but TSMC N3 for the large iGPU. Anywho, the transistor density of TSMC's N2 node is dramatically higher than its N4 node.

Current rumours suggest that the big Nova Lake CPU die will contain 144 MB of bLLC cache. The AMD Ryzen 9800X3D currently has 64 MB of L3 memory in the V-cache slice, plus another 32 MB on-die. Of course, AMD will likely have its own upgraded Zen 6-based CPUs with even more V-cache around the time that Nova Lake is made available.

Anywho, Nova Lake is supposedly due out later this year, though for now it's not clear whether these purported bLLC models will be available from day one. On paper, they should be the most compelling Nova Lake models from a gaming perspective, as implied by the outstanding gaming performance of AMD's X3D chips.

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Jeremy Laird
Jeremy Laird
Hardware writer

Jeremy has been writing about technology and PCs since the 90nm Netburst era (Google it!) and enjoys nothing more than a serious dissertation on the finer points of monitor input lag and overshoot followed by a forensic examination of advanced lithography. Or maybe he just likes machines that go “ping!” He also has a thing for tennis and cars.

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