A patent suggests AMD is getting inventive to meet Intel and Arm in mobile devices

(Image credit: AMD)

AMD has patented a multi-core hybrid computing architecture that's somewhat analogous to Arm's big.LITTLE approach, or Intel's Lakefield chip. While by no means a confirmation of what's to come from the red team, the patent suggests there's definitely some interest in pursuing a processor that mixes the best of both high-power and low-power computing all at once.

We now live in an age where it's totally acceptable to stuff 10, 12, or 16 cores into a processor and call it a day. AMD and Intel are both at it as they wrestle for the multi-core performance crown. Yet these chips are the antithesis of efficiency, and there's a need for some workloads to offer both hefty single-core performance without cranking up the power draw.

Enter: the hybrid chip. It's an approach championed, or at least most widely utilised, under the big.LITTLE banner. This is a heterogeneous processing architecture laid out by Arm, whose 'big' processors are designed to do the computationally heavy work, while its 'LITTLE' processors are designed to take care of everything else with maximum power efficiency. 

Intel has also followed suit with its Lakefield chip, an amalgamation of both a big Core core and a little Atom core, and is also expected to do so with its broader Alder Lake desktop architecture of the future.

New patents dug out by user Underfox3 on Twitter, via freepatentsonline [PDF warning], suggest that AMD is at least considering a heterogeneous approach of its own. The patent was first filed back in 2017, and so is only relatively new to us lot. Over at AMD it's likely been a consideration for R&D for some time.  

The patent titled 'Instruction subset implementation for low power operation' is relatively basic. It outlines how two processors, one labelled 'high-feature' and another labelled 'low-feature' would communicate and divvy up tasks between them for efficient operation.

Three potential designs are outlined within the patent, and each one differs in cache configuration and shared registers. All possible outcomes share a similar goal, however: when the low-power chip is over-utilised, the execution of a given thread is handed over to the high-performance chip.

The patent specifically outlines the growing need for such a chip in mobile devices, in order to conserve battery life, and thus it's not expected to reach the desktop processor market anytime soon.

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Yet rumours have suggested that Intel may be looking to a hybrid computing solution for future desktop chips, even as early as Alder Lake on 10nm in 2021. This chip would use eight Golden Cove cores, an evolution of Tiger Lake's Willow Cove cores, and eight lower-performance Gracemont cores, according to reports. It's hard to imagine to what end such a chip would be useful on desktop when battery conservation isn't a concern, but if it's true then one can assume Intel's engineers have faith in the concept.

Yet PC power draw cannot keep growing exponentially, and while process node development is still trucking on moderately well today (for some) we will reach a point when smarter, heterogeneous chips are required to meet users requirements and do so without sapping exorbitant power from the mains.

And speaking of patents, Underfox has also been busy digging out a whole heap of AMD's, including everything from spring-loaded heat spreaders to neural network chomping circuits. It's impossible to predict which, if any, will ever make it to a shipping processor, but it makes for good future-gazing if you're into that sort of thing.

Jacob Ridley
Senior Hardware Editor

Jacob earned his first byline writing for his own tech blog. From there, he graduated to professionally breaking things as hardware writer at PCGamesN, and would go on to run the team as hardware editor. Since then he's joined PC Gamer's top staff as senior hardware editor, where he spends his days reporting on the latest developments in the technology and gaming industries and testing the newest PC components.