Intel's Arrow Lake chips could be using a brand new core layout for the first time in years

Intel Meteor Lake CPU
(Image credit: Intel)

After years of using the same fundamental layout of processing cores in its desktop CPUs, it looks like Intel will mix things up a little with its forthcoming Arrow Lake architecture. Instead of two rows of main, or Performance-cores, followed by several banks of Efficient-cores in recent designs, Arrow Lake might switch to a repeated sequence of blocks, containing four P-cores and two banks of four E-cores. And it could all be down to the use of rentable units.

The idea that Intel might be changing how it lays out cores in its processors has been suggested by Kepler_L2 on X and then confirmed by Bionic_Squash, two people who are well-regarding for being pretty accurate in terms of leaks and industry rumours.

The block diagram in the post is a mock-up of the P- and E-core arrangement that Intel is reportedly going to use in Arrow Lake and shows the design uses a repeated pattern of four P-cores surrounding two banks of four E-cores.

That's markedly different to how the cores are in the latest architectures, Meteor Lake and Raptor Lake Refresh—if the diagram is correct then it would be the first big change in core layout since Intel introduced the E-core in its desktop chips in Alder Lake in 2021. In fact, Intel's layouts have barely changed since Sandy Bridge in 2011, as the format has worked very well.

Back then, the likes of the Core i7 2700K had four cores in a row, all connected to a ring bus that allowed fast access to the shared L3 cache. Over successive generations of chip designs, Intel added more cores just by making the row longer and then adding a second row. The last architecture before the hybrid era, Rocket Lake in 2021, comprised two rows of four cores, with the bus in between the rows.

That didn't change with the introduction of E-cores with Alder Lake, as they were simply added at the end of P-core rows, with the ring bus made longer to accommodate them. It's still like that now in Raptor Lake Refresh, and even the small compute tile in Meteor Lake laptop CPUs is laid out this way.

However, Kepler_L2's diagram is notably different to this but the obvious question to ask is: why? One possibility is that this is simply about layout efficiency, reducing hot spot temperatures, current leakage, and core-to-core latencies. But the scale of the change suggests that it might be more significant than this and the other possible explanation is that Intel could be roadtesting its Rentable Units (RU) idea in Arrow Lake.

An annotated die shot of a Core i9 13900K showing the rows of P-cores and E-cores (Image credit: JmsDoug / Fritzchen Fritz)

This is something Intel patented a while back and it's essentially a complex circuit that partitions threads, based on instruction complexity, and issues those partitions to the appropriate P- or E-core, depending on what needs to be processed in that partition.

By having a single block of four P-cores and eight E-cores, Intel could have designed Arrow Lake such that each block has its own RU, creating something relatively easy to scale. The lowest tier models would have one or two blocks, with some cores disabled, whereas the highest spec processors could sport four or more blocks.

Intel will also want to make full use of its Skymont E-core design in Arrow Lake. The new efficiency cores are claimed to have a greater IPC (instruction rate per clock) than Raptor Lake's P-cores, which is why Intel didn't furnish Lunar Lake's P-cores with any HyperThreading (HT) hardware.

It's been rumoured for a while that Arrow Lake also won't sport HT as well so a 15th Gen Core processor with eight P-cores and 16 E-cores, would only be a 24-thread chip. That's quite a drop from the 32 supported by the Core i9 14900K so I can't see Intel doing this for the high-end Arrow Lake desktop CPUs.

However, it might do it for lower-tier models, such as the i7 and i5, to help make the most powerful processors stand out more. Then again, it doesn't make much sense to use RU and HT at the same time, as the general idea is that the former is more flexible than the latter.

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Of course, two people on social media saying this is what Arrow Lake's core layout is like is by no means concrete evidence of the change, nor is it fully indicative that Rental Units are on their way.

But all of it is true and Intel has worked on improving how its P- and E-cores are utilised, then the changes will be very welcome, especially given how much Intel has improved its efficiency cores for Lunar Lake.

For PC gaming, it probably won't make much of a difference, as six to eight P-cores with HyperThreading are still more than enough for the vast majority of games out there, but for content creation, better multi-threaded performance is a must.

This is particularly important as AMD Zen 5-powered 16-core Ryzen processors will be on the market very soon and will almost certainly set a new bar for multi-core speed.

Nick Evanson
Hardware Writer

Nick, gaming, and computers all first met in 1981, with the love affair starting on a Sinclair ZX81 in kit form and a book on ZX Basic. He ended up becoming a physics and IT teacher, but by the late 1990s decided it was time to cut his teeth writing for a long defunct UK tech site. He went on to do the same at Madonion, helping to write the help files for 3DMark and PCMark. After a short stint working at, Nick joined Futuremark (MadOnion rebranded) full-time, as editor-in-chief for its gaming and hardware section, YouGamers. After the site shutdown, he became an engineering and computing lecturer for many years, but missed the writing bug. Cue four years at and over 100 long articles on anything and everything. He freely admits to being far too obsessed with GPUs and open world grindy RPGs, but who isn't these days?